Cavium Inc., a leader in multicore security and network processors, has introduced a new version of its Octeon processor family, based on the MIPS RISC instruction set.  Octeon Fusion is optimized for high-performance base station applications, combining up to six 64-bit MIPS cores with multiple baseband DSP cores, the latter optimized for the algorithms used in 3G and 4G Long-Term Evolution cellular networks.

Because of the high integration and low power dissipation, Octeon Fusion can be used in micro-cell and picocell base stations, where space is at a premium.  The Fusion family members can be used in stations that support 32 to 300 more cellular users, while handling dual 20-MHz carriers.

Octeon Fusion processors ship with the FusionStack software, providing fully configured Layer 1 to Layer 3 software for cellular applications.  The cores are compatible with earlier Octeon families, allowing easy migration from older designs.  Octeon will demonstrate the first working samples of Octeon Fusion at the 4G World Congress, held Oct. 25-27 in Chicago.